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IBM TO FOLD MAINFRAMES INTO POWER LINE WITH z6

Last August, IBM began talking to various interested parties about the chips that will power a future generation of mainframe called the z6. That future generation is probably the next generation, the one that follows the current z9 product line.  The chips are called z6 because they are part of the Power 6 family.  IBM is out preparing customers for the change because it is concerned about the reception its future mainframes will receive.  And well it should be.

During the third quarter, as IBM was taking its z6 slide show on the road, mainframe revenue fell 31 percent.  While IBM executives have said, optimistically, that they believe the downturn will prove to be a deferral of orders rather than a permanent decline, chances are they don't actually know what the future will bring.  But it's a safe bet that it won't bring huge demand for machines that are clearly nearing the end of their production cycle.  It's also pretty obvious that IBM's z6 mainframes, based on substantially different chip technology than current and recent machines, will have to win user acceptance, which might take some time.  Basically, IBM is about to begin a major product transition, the most significant since it leapt from bipolar technology to CMOS in 1994.  This jump ought to be easier, but moving a mainframe to RISC is not without risk.

IBM's Power 6 chips run at a much higher clock rate than current mainframe processors.  The ones in the z6 are expected to run at more than 4 GHz, a big jump from the 1.7 GHz clock rate of the fastest z9 engines.  But that doesn't mean the new mainframe motors will be twice as powerful as current ones, because the new architecture breaks any connection between chip speed and MIPS that was characteristic of the outgoing processor technology.

When it ultimately reveals the performance of the first round of z6 machines, IBM might boast of higher MIPS per engine, but it might also say its first Power machines are only the rough equals of their CISC predecessors .  .  .  or even that the z6 mainframes will require more engines to deliver the same performance as their predecessors.

So far, there are three clues about IBM's z6 engine power.  One is the absence of any mention of in Big Blue's slide show of processor performance in MIPS or MSU.  The second is a complete lack of information on z6 channel technology; IBM's System p machines don't have channels.  The third is history: It took IBM quite a while to get its 9672 CMOS circuits to outrun the bipolar machines they supplanted.  In fact, it took IBM a whole six-way 9672-G1 to provide the MIPS of its best single-engine 9021.  IBM's CMOS engines didn't exceed the power of bipolar mainframe engines until their fourth generation.

Not only did IBM have a hard time beating bipolar performance with CMOS, it also had to persuade customers that its mainframe hardware and software would evolve to provide the illusion of a huge single processor image even when the underlying system had many engines.

This kind of problem might not be a show-stopper for Google, which can throw a zillion X86 Linux boxes at problems it defines along the way, but it's a tough challenge for IBM's mainframe division, which has to give customers leading edge solutions to age old data processing problems (and age-old code, too).

While there's little doubt IBM will solve any problems that arise as it moves from z9a to Power z6, there's every reason for users who like to plan ahead to worry about when and how Big Blue will address the perpetual challenge faced by mainframe shops, which is now to get sufficient value from big iron.

The value question is going to become more interesting as IBM rolls out z6.

The memory in a z6 mainframe will most likely be the same as the memory in big System p Unix boxes based on Power 6 technology.  If the memory isn't the same, IBM's Unix rivals like HP will be able to ask prospective buyers of IBM p machine why they are settling for second best.  Okay, maybe IBM will find some wiggle room in the memory department by saying that the way mainframes use memory is not the same as the way Unix systems use memory and thereby justify some differences in technology and price.  But it's going to be a hard argument to sustain when a site is trying to decide between mainframe and Unix flavors of some applications software and IBM starts to look confused as it competes with itself.

On the other hand, IBM ought to have an easy time getting z/Linux or maybe just plain Linux to really fly on the z6 boxes compared to the way it runs on today's mainframes.  After all, the Power chips are designed to run 'nix code.  Still, there could be differences in Linux performance on z6 versus p6 machines even though the two server lines are based on the same generation of Power chips.

IBM is going to add some features to the Power Unix engine as it turns it into a mainframe engine, stuff that is a lot more than just tuning.  Silicon real estate, unlike the other kind of real estate that caused the mainframe business to fade last quarter, is always at a premium.  If IBM adds stuff to the Power chip, it might also have to take some away.  In addition, there are real software differences between Linux on a z and Linux on a p; mainframe shops generally run z/Linux inside VM, building bridges between Linux and z/OS but adding overhead, too.

Still, even if the z6 is a killer when it comes to Linux, it has to deliver good performance and good value when it runs CICS, DB2, and the diverse collection of legacy applications that mainframe shops support.  And it just might not do that, at last at first.

There are substantial differences between CISC architectures, like that of the established z machines, and RISC architectures, like that of the Power chips.  For one thing, RISC machines are optimized for fixed-length instructions, while instructions on CISC machines vary in length.  When IBM migrated its proprietary midrange systems from CISC to RISC processor technology, it built quite a lot of translation technology.  Even so, users who wanted to get the most out of their machines had to recompile their applications.

Nobody is more concerned with system efficiency than mainframe users.  Their machines are hugely expensive, resources no company can afford to waste.  IBM has been able to get a phenomenal premium for mainframe hardware, software, and services because the talent pool surrounding big iron is great at squeezing the most out of the machines.  Consequently, telling the mainframe user base that the next generation of mainframes might not be very efficient is not the sort of thing IBM can very easily do.  But it just might have to.

Perhaps IBM can get its z6 engines to run legacy binaries at acceptable speed.  Perhaps Charles Webb can make the z6 chip a real winner.  Webb is the IBM fellow whose decimal floating point hardware is one of the key features in all Power 6 chips.  In the past, Webb's work on IBM central processors helped Big Blue dig itself out of the performance deficit that arose when mainframes went from bipolar to CMOS technology.

So far, however, Webb is talking about gates and bandwidth and transistors, but not about MIPS, I/Os, or transactions per second.

— Hesh Wiener October 2007


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